The present invention relates to a semiconductor memory device, and more particularly, to a circuit for generating an address of a semiconductor memory device, which improves usage yield of the semiconductor memory device.
A related art circuit for generating an address of a semiconductor memory device will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a related art circuit for generating an address of a semiconductor memory device, FIG. 2 shows a refresh counting unit of FIG. 1, and FIG. 3 shows an address switching unit of FIG. 1.
As shown in FIG. 1, the related art circuit for generating an address of a semiconductor memory device includes a refresh counting unit 11 outputting an n-bit refresh address BX signals in response to a refresh enable signal REN to refresh an address; an address buffer 13 outputting an n-bit input address AX signals in response to an external address EXa; and an address switching unit 13 selecting either the BX or the AX signals and outputting bank address and internal address (BA and Int) signals in response to the REN signal.
As shown in FIG. 2, the refresh counting unit 11 includes n refresh counters 200 to 20nxe2x88x921 outputting BX signals BX[0] to BX[nxe2x88x921], respectively, to the address switching unit 13 when enabled by the refresh enable signal REN. The refresh counters 200 to 20nxe2x88x922 also output carry signals C0 to Cnxe2x88x922, where each carry signal is received by the respective higher order bit neighboring refresh counters 201 to 20nxe2x88x921.
The address switching unit 13, as shown in FIG. 3, includes n switches 300 to 30nxe2x88x921 to select either the n-bit BX or AX signals to output as internal addresses Int[0] to Int[nxe2x88x921]. The selection is performed in response to the refresh enable REN signal.
The operation of the aforementioned related art circuit for generating an address of a semiconductor memory device will be described below.
When no refresh operation takes place, i.e., when the REN is disabled, the address switching unit 13 selects the AX signals from the address buffer 12 to be output as the Int signals. However, when the refresh operation does take place, i.e., when the REN is enabled, the address switching unit 13 selects the BX signals from the refresh counting unit 11.
The above mentioned related art circuit for generating an address of a semiconductor memory device has at least the following problem. When there are errors in any part of the memory device, the entire device must be discarded. This is even if a majority of the sections of the device may be properly functioning. This reduces the usage yield of the semiconductor memory device since the usable sections of the memory are also discarded, and thus increases the production cost due to the unnecessary discarding of useful devices.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a circuit for generating an address of a semiconductor memory device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a circuit for generating an address of a semiconductor memory device, which improves yield of the semiconductor memory device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve at least these objects and other advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, a circuit for generating an address of a semiconductor memory device includes a half chip enable unit receiving a half chip enable signal for allowing a memory cell having a defect to be constructed by a half chip; a refresh counting unit generating a refresh address in response to an external refresh enable signal and the half chip enable signal; an address buffer receiving an external address and generating an input address; an address switching unit selectively outputting one of the refresh address and the input address as an internal address in response to the refresh enable signal and the half chip enable signal; a block fail determining unit outputting a block fail signal data indicating a poor memory cell in response to the half chip enable signal; and a bank address coding unit generating a bank address using the refresh address and performing a logic operation of an output signal of the block fail determining unit and a bank address when the half chip enable signal is enabled in a half chip operation, to output the logic operated signal to a coded bank address of the defected memory cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.